CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 76.
45. lappuse
Hardware Support for Real - time Operating Systems Table 1. RTOS Function Details Implementation / Overhead Unsorted Ready. Paul Kohout1 EVI Technology , LLC . 7138 Columbia Gateway Dr. Columbia Maryland 21046 pkohout@evitechnology.com 1 ...
Hardware Support for Real - time Operating Systems Table 1. RTOS Function Details Implementation / Overhead Unsorted Ready. Paul Kohout1 EVI Technology , LLC . 7138 Columbia Gateway Dr. Columbia Maryland 21046 pkohout@evitechnology.com 1 ...
114. lappuse
... Time Task Scheduling. ABSTRACT Current methods cannot synthesize real - time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical path in the task . This ...
... Time Task Scheduling. ABSTRACT Current methods cannot synthesize real - time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical path in the task . This ...
116. lappuse
3. SOFTWARE SYNTHESIS Our target is the formal synthesis of real - time embedded soft- ware , with local and global deadlines , using scheduling techniques . A system is specified as a set of concurrent tasks , where each task is ...
3. SOFTWARE SYNTHESIS Our target is the formal synthesis of real - time embedded soft- ware , with local and global deadlines , using scheduling techniques . A system is specified as a set of concurrent tasks , where each task is ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires