CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 90.
100. lappuse
... processor then determines the best motion vector , does a refinement , and transmits the results back to software . Further , in software , the encoding mode is selected , and the quantizer value is computed . The quantizer value and ...
... processor then determines the best motion vector , does a refinement , and transmits the results back to software . Further , in software , the encoding mode is selected , and the quantizer value is computed . The quantizer value and ...
219. lappuse
... processor DSPs . It integrates a novel data transformation technique that ex- poses the processor location of partitioned data into a par- allelization strategy . When this is combined with a new ad- dress resolution mechanism , it ...
... processor DSPs . It integrates a novel data transformation technique that ex- poses the processor location of partitioned data into a par- allelization strategy . When this is combined with a new ad- dress resolution mechanism , it ...
220. lappuse
... processor and memory location of all items . 2.1 Example INTERNAL SPACE GLOBAL SPACE Host Memory Block 1 Memory Block 0 SDRAM 0x001807FF Internal Registers RESERVTE Internal Memory 2 0x00180000 Processor ID 7 Processor ID & Processor ID 5 ...
... processor and memory location of all items . 2.1 Example INTERNAL SPACE GLOBAL SPACE Host Memory Block 1 Memory Block 0 SDRAM 0x001807FF Internal Registers RESERVTE Internal Memory 2 0x00180000 Processor ID 7 Processor ID & Processor ID 5 ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires