CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 44.
43. lappuse
... priority definition agrees with operating system code execution level definition , S1 , C3 and C4 guarantee E2 and ... priority p . Define W , as the longest execution time of the code executing at priority p without processing a new ...
... priority definition agrees with operating system code execution level definition , S1 , C3 and C4 guarantee E2 and ... priority p . Define W , as the longest execution time of the code executing at priority p without processing a new ...
47. lappuse
... priority and event ID fields are each 8 bits wide and the delay field is 16 bits wide . Each record uses 40 bits of ... Priority Test cell . Each Nth order Priority Test cell contains an 8 - bit comparator , an 8 - bit 2 : 1 MUX , an ( N ...
... priority and event ID fields are each 8 bits wide and the delay field is 16 bits wide . Each record uses 40 bits of ... Priority Test cell . Each Nth order Priority Test cell contains an 8 - bit comparator , an 8 - bit 2 : 1 MUX , an ( N ...
48. lappuse
... priority scheduling . The RTM queries for the highest priority task that is pending on a given event identifier , instead of querying its data structure for the highest priority ready task . 5. ARCHITECTURE A reference architecture is ...
... priority scheduling . The RTM queries for the highest priority task that is pending on a given event identifier , instead of querying its data structure for the highest priority ready task . 5. ARCHITECTURE A reference architecture is ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires