CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 62.
16. lappuse
... presented in lines 5-10 in Figure 6 . Finally for sixteen instructions in this group we need at least 16x10x5 = 800 lines in the LISA description . As shown in Figure 4 , in our mode , this group of instructions is represented by only ...
... presented in lines 5-10 in Figure 6 . Finally for sixteen instructions in this group we need at least 16x10x5 = 800 lines in the LISA description . As shown in Figure 4 , in our mode , this group of instructions is represented by only ...
91. lappuse
... presented in [ 13 ] [ 8 ] . This work focuses on deriving Kahn Process Network ( KPN ) specifications from applications described as static parameterized affine nested loop programs . In contrast , the work presented in this paper deals ...
... presented in [ 13 ] [ 8 ] . This work focuses on deriving Kahn Process Network ( KPN ) specifications from applications described as static parameterized affine nested loop programs . In contrast , the work presented in this paper deals ...
96. lappuse
... presented in this paper support FIFO merging by grouping edges as discussed in Section 3.4 . However , the selection of channels to be merged is currently still the design- ers choice . 5. CONCLUSIONS In this paper , we presented a ...
... presented in this paper support FIFO merging by grouping edges as discussed in Section 3.4 . However , the selection of channels to be merged is currently still the design- ers choice . 5. CONCLUSIONS In this paper , we presented a ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires