CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 29.
39. lappuse
... port accesses ( read and write ) of a single channel are concurrent . The data channel is shared at the granularity of a data unit . Three data port access modes are defined : blocked , buffered , and asynchronous . Blocked and buffered ...
... port accesses ( read and write ) of a single channel are concurrent . The data channel is shared at the granularity of a data unit . Three data port access modes are defined : blocked , buffered , and asynchronous . Blocked and buffered ...
93. lappuse
... port to the node domain . Ap is a variable binding the port to IPDs of other ports if A , & in ^ Ap ‡ Vp . IPDp is the input port domain of p defined by a LBS ( Definition 3.6 ) . Definition 3.4 ( output port ) = An output port is given ...
... port to the node domain . Ap is a variable binding the port to IPDs of other ports if A , & in ^ Ap ‡ Vp . IPDp is the input port domain of p defined by a LBS ( Definition 3.6 ) . Definition 3.4 ( output port ) = An output port is given ...
94. lappuse
... ports connected to a single output port . On the other hand , we focus on the synthesis of a special class of process net- works - Kahn Process Networks where every input port has to be connected to only one unique output port . This ...
... ports connected to a single output port . On the other hand , we focus on the synthesis of a special class of process net- works - Kahn Process Networks where every input port has to be connected to only one unique output port . This ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires