CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 19.
84. lappuse
... phase Dynamic phase Static phase communication controller Dynamic phase m2 T1,2 T1.4 $ 12.2 ST : T2.3 m1 , m3 T2,2 DYN : m2 , m4 DYN msg DYN msg slot 3 slot 2 slot 1 DYN msg DYN msg DYN msg slot 7 slot 6 slot 5 slot 4 Figure 1. System ...
... phase Dynamic phase Static phase communication controller Dynamic phase m2 T1,2 T1.4 $ 12.2 ST : T2.3 m1 , m3 T2,2 DYN : m2 , m4 DYN msg DYN msg slot 3 slot 2 slot 1 DYN msg DYN msg DYN msg slot 7 slot 6 slot 5 slot 4 Figure 1. System ...
86. lappuse
... phase ( dy- namically scheduled ) . In order to keep the presentation reasonably simple and given the space ... phase to the length of the largest DYN message LDN The number n of dynamic phases in each cycle can be determined from the ...
... phase ( dy- namically scheduled ) . In order to keep the presentation reasonably simple and given the space ... phase to the length of the largest DYN message LDN The number n of dynamic phases in each cycle can be determined from the ...
88. lappuse
... phase ( line 6 ) includes also the value 0. Therefore , in the final bus cycle , it is not needed that each static slot is followed by a dynamic phase ( see also Figure 1 ) . Dynamic phases introduced as result of the pre- vious steps ...
... phase ( line 6 ) includes also the value 0. Therefore , in the final bus cycle , it is not needed that each static slot is followed by a dynamic phase ( see also Figure 1 ) . Dynamic phases introduced as result of the pre- vious steps ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires