CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 86.
5. lappuse
... Performance improvement due to OS modeling A Modular Simulation Framework for Architectural Exploration of On -. gain of the proposed approach against the case when RTOS is actually executed on the ISS . 6. EXPERIMENTS In this section ...
... Performance improvement due to OS modeling A Modular Simulation Framework for Architectural Exploration of On -. gain of the proposed approach against the case when RTOS is actually executed on the ISS . 6. EXPERIMENTS In this section ...
139. lappuse
... performance and cost . However , as mobile systems evolve into data centric and multimedia - oriented applications , storage with high performance and huge capacity has become necessary . The second architecture ( Figure 1 ( b ) ) seems ...
... performance and cost . However , as mobile systems evolve into data centric and multimedia - oriented applications , storage with high performance and huge capacity has become necessary . The second architecture ( Figure 1 ( b ) ) seems ...
152. lappuse
3.2 Performance Analysis System performance is often the most important factor used for deciding the architecture of an SoC . The overall performance of a system is dependent on the raw performance of individual components and on the ...
3.2 Performance Analysis System performance is often the most important factor used for deciding the architecture of an SoC . The overall performance of a system is dependent on the raw performance of individual components and on the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires