CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 37.
86. lappuse
... partitioning of a certain task , the whole task graph is assigned to either the TT or ET domain . A similar partitioning problem , as formulated above for tasks , could be also defined at the level of messages : considering a set of ...
... partitioning of a certain task , the whole task graph is assigned to either the TT or ET domain . A similar partitioning problem , as formulated above for tasks , could be also defined at the level of messages : considering a set of ...
92. lappuse
... partitioning information . Such information can be given manually or delivered by the partitioning information box shown in Figure 2. This box implements some design space exploration procedures and / or some optimization procedures ...
... partitioning information . Such information can be given manually or delivered by the partitioning information box shown in Figure 2. This box implements some design space exploration procedures and / or some optimization procedures ...
109. lappuse
... partitioning . These new uses require logic minimization to run dynamically as part of an embedded system's active ... partitioning , dynamically reducing network routing table size , and dynamically reducing network access control lists ...
... partitioning . These new uses require logic minimization to run dynamically as part of an embedded system's active ... partitioning , dynamically reducing network routing table size , and dynamically reducing network access control lists ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires