CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 43.
53. lappuse
... Parallel Reed - Solomon Decoder On a Reconfigurable. ABSTRACT This paper describes a hardware - software co - design approach for flexible programmable Galois Field Processing for applications which require operations over GF ( 2 ...
... Parallel Reed - Solomon Decoder On a Reconfigurable. ABSTRACT This paper describes a hardware - software co - design approach for flexible programmable Galois Field Processing for applications which require operations over GF ( 2 ...
90. lappuse
... parallel multi - processor architec- ture very difficult . On the other hand , if the application is specified using a parallel model of computation ( MoC ) then the mapping will be done in a systematic and transparent way using a ...
... parallel multi - processor architec- ture very difficult . On the other hand , if the application is specified using a parallel model of computation ( MoC ) then the mapping will be done in a systematic and transparent way using a ...
107. lappuse
... parallel . Finally , at the algorithm level , the asymptotic behavior of the VA can be exploited to derive parallel processing architectures [ 9 ] . The bit level parallelism can be incorporated into almost any arithmetic logic unit ...
... parallel . Finally , at the algorithm level , the asymptotic behavior of the VA can be exploited to derive parallel processing architectures [ 9 ] . The bit level parallelism can be incorporated into almost any arithmetic logic unit ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires