CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 22.
11. lappuse
... Packet Bus DRAM MMU Figure 4 : a ) Intel IXP2400 Mapping the weighted RED algorithm [ 29 ] to avoid throughput degradation in a TCP friendly manner due to congestion . The Queuer stores IP packets according to their COS until they can ...
... Packet Bus DRAM MMU Figure 4 : a ) Intel IXP2400 Mapping the weighted RED algorithm [ 29 ] to avoid throughput degradation in a TCP friendly manner due to congestion . The Queuer stores IP packets according to their COS until they can ...
172. lappuse
... packets . A packet consists of a start bit , followed by two bits indicating yes / no / error , followed by several stop bits . In the future , we will incorporate identification information into the packet . A block can also transmit ...
... packets . A packet consists of a start bit , followed by two bits indicating yes / no / error , followed by several stop bits . In the future , we will incorporate identification information into the packet . A block can also transmit ...
226. lappuse
... packet size . The packet sizes of both local area networks and wide area networks conform to bimodal distribution [ 20 ] . We analyze traffic traces available from NLANR for both local area networks ( LAN ) and wide area networks ( WAN ) ...
... packet size . The packet sizes of both local area networks and wide area networks conform to bimodal distribution [ 20 ] . We analyze traffic traces available from NLANR for both local area networks ( LAN ) and wide area networks ( WAN ) ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires