CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 35.
4. lappuse
... overhead of kernel mode associated with tick interrupt handling and context switching . We denoter as the ratio of this overhead to the total simulation time . If the tick interrupt overhead dominates the context switch overhead , as ...
... overhead of kernel mode associated with tick interrupt handling and context switching . We denoter as the ratio of this overhead to the total simulation time . If the tick interrupt overhead dominates the context switch overhead , as ...
46. lappuse
... overhead , Task Insertion on Ready Queue has Linear Overhead Constant Overhead implementation for systems with unique and static priorities . Each task has individual delay counter containing its absolute delay . Timer Update requires ...
... overhead , Task Insertion on Ready Queue has Linear Overhead Constant Overhead implementation for systems with unique and static priorities . Each task has individual delay counter containing its absolute delay . Timer Update requires ...
50. lappuse
... overhead associated with communicating the request to the RTM . The category of processing clock ticks execute at the same instances as polling . But in this case , the RTM reduces the magnitude of the overhead by around 85 % . Both ...
... overhead associated with communicating the request to the RTM . The category of processing clock ticks execute at the same instances as polling . But in this case , the RTM reduces the magnitude of the overhead by around 85 % . Both ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires