CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 44.
93. lappuse
... output and they play a role in the conversion of a dSAC to an approximated dependence graph presented in the next section . 3.2 Approximated Dependence Graph In this section we give a formal definition of our Approximated Dependence ...
... output and they play a role in the conversion of a dSAC to an approximated dependence graph presented in the next section . 3.2 Approximated Dependence Graph In this section we give a formal definition of our Approximated Dependence ...
171. lappuse
... output . An input of yes toggles ( inverts ) the current value outputted by the device . Configurable logic block programmed by the user via DIP switch . Figure 3 : eBlock Systems : ( a ) Garage. Communication / logic Output Sensor O O O ...
... output . An input of yes toggles ( inverts ) the current value outputted by the device . Configurable logic block programmed by the user via DIP switch . Figure 3 : eBlock Systems : ( a ) Garage. Communication / logic Output Sensor O O O ...
172. lappuse
... Output Block - Green / Red LED eBlock ( a ) IX rx ( b ) 4.2 Computers in Every Block ( c ) We quickly determined that communication of logic values among eBlocks could not be implemented directly as a physical wire carrying 1 for yes ...
... Output Block - Green / Red LED eBlock ( a ) IX rx ( b ) 4.2 Computers in Every Block ( c ) We quickly determined that communication of logic values among eBlocks could not be implemented directly as a physical wire carrying 1 for yes ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires