CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 87.
144. lappuse
... Optimization and Space Minimization ( IDOM ) towards finding the minimum configuration satisfying timing and code size constraints . We show an effective way to reduce the design space to be explored through the study of the fundamental ...
... Optimization and Space Minimization ( IDOM ) towards finding the minimum configuration satisfying timing and code size constraints . We show an effective way to reduce the design space to be explored through the study of the fundamental ...
145. lappuse
... OPTIMIZATION TECHNIQUES AND DE- SIGN SPACE MINIMIZATION In this section , we present the the theoretical foundation of the integrated framework for design optimization and space minimiza- tion . We provide an overview of the basic ...
... OPTIMIZATION TECHNIQUES AND DE- SIGN SPACE MINIMIZATION In this section , we present the the theoretical foundation of the integrated framework for design optimization and space minimiza- tion . We provide an overview of the basic ...
182. lappuse
... optimization problem . For a solution approach , an optimization software tool , implementing an evolu- tionary algorithm from the literature , has been developed to achieve a set of best alternative mapping decisions under multiple ...
... optimization problem . For a solution approach , an optimization software tool , implementing an evolu- tionary algorithm from the literature , has been developed to achieve a set of best alternative mapping decisions under multiple ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires