CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 72.
15. lappuse
... operations in the instruction set . 3.3 Generating Fast Code for Simulators Typically in simulators , for each ... operations of ARM * / template < class Conditions , class Operations , class ShifterOperand , bool updateFlag > class ...
... operations in the instruction set . 3.3 Generating Fast Code for Simulators Typically in simulators , for each ... operations of ARM * / template < class Conditions , class Operations , class ShifterOperand , bool updateFlag > class ...
128. lappuse
... Operations in the top level of the CG ; for each set of operations Oij Є Ocg do % Oij is the set of operations of same type j at level i that can be assigned to the same module ; CMPsch , CMDsch ← Payoff matrix ( O1j , Mij , i ) ...
... Operations in the top level of the CG ; for each set of operations Oij Є Ocg do % Oij is the set of operations of same type j at level i that can be assigned to the same module ; CMPsch , CMDsch ← Payoff matrix ( O1j , Mij , i ) ...
129. lappuse
... operations to choose the modules such that power minimization is achieved . Normally , in a bid , the bidder has a ... operations scheduled during control step i architecture number of operations of type j in the architecture set of all ...
... operations to choose the modules such that power minimization is achieved . Normally , in a bid , the bidder has a ... operations scheduled during control step i architecture number of operations of type j in the architecture set of all ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires