CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 18.
26. lappuse
... object - oriented hardware design . Some of these approaches are based on object - oriented programming lan- guages and augment them by capabilities for hardware mod- elling [ 4 , 3 , 15 ] , whilst other approaches are based on exist ...
... object - oriented hardware design . Some of these approaches are based on object - oriented programming lan- guages and augment them by capabilities for hardware mod- elling [ 4 , 3 , 15 ] , whilst other approaches are based on exist ...
28. lappuse
... object is , in principle , an object which is declared as member of a SystemC module , like a port or signal . Therefore it is visible and accessible by all processes declared in the same module . Like any other object a global object ...
... object is , in principle , an object which is declared as member of a SystemC module , like a port or signal . Therefore it is visible and accessible by all processes declared in the same module . Like any other object a global object ...
215. lappuse
... object objects are not necessarily aligned to the beginning of cache lines , it is possible for multiple objects to be contained in the same cache line . Further , these multiple objects can be in different phases of their lives . For ...
... object objects are not necessarily aligned to the beginning of cache lines , it is possible for multiple objects to be contained in the same cache line . Further , these multiple objects can be in different phases of their lives . For ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires