CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 62.
182. lappuse
... multiple criteria to consider , like processing times , power consumption and cost of the architecture , which make the decision problem even harder . In this paper , the mapping decision problem is formulated as a multiobjective ...
... multiple criteria to consider , like processing times , power consumption and cost of the architecture , which make the decision problem even harder . In this paper , the mapping decision problem is formulated as a multiobjective ...
189. lappuse
... multiple wires and last multiple bus cycles . Furthermore , arbitrary effects of faults can be represented . We show that accurate prediction of error probabilities can be achieved by an estimation method based on this nota- tion which ...
... multiple wires and last multiple bus cycles . Furthermore , arbitrary effects of faults can be represented . We show that accurate prediction of error probabilities can be achieved by an estimation method based on this nota- tion which ...
219. lappuse
... multiple address space , multi - processor DSPs . It integrates a novel data transformation technique that ex- poses the processor location of partitioned data into a par- allelization strategy . When this is combined with a new ad ...
... multiple address space , multi - processor DSPs . It integrates a novel data transformation technique that ex- poses the processor location of partitioned data into a par- allelization strategy . When this is combined with a new ad ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires