CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 8.
97. lappuse
... ( minimal flexibility ) and control - intensive tasks onto software ( maximal flexibility ) . The encoder uses an architecture template C - HEAP ( CPU - controlled Heterogeneous Embedded Architectures for signal Processing [ 5 ] ...
... ( minimal flexibility ) and control - intensive tasks onto software ( maximal flexibility ) . The encoder uses an architecture template C - HEAP ( CPU - controlled Heterogeneous Embedded Architectures for signal Processing [ 5 ] ...
170. lappuse
... minimal set of eBlocks , and introduced new eBlocks , or added features to an existing eBlock , only when building an application with the minimal set seemed to be too difficult for an ordinary user . Below are the eBlocks we defined ...
... minimal set of eBlocks , and introduced new eBlocks , or added features to an existing eBlock , only when building an application with the minimal set seemed to be too difficult for an ordinary user . Below are the eBlocks we defined ...
223. lappuse
... minimal number of barrier synchronizations [ 15 ] . 4. EXPERIMENTAL FRAMEWORK The best publicly available , auto - parallelizing , C com- piler SUIF produces shared - memory data parallel C codes from sequential C input files and ...
... minimal number of barrier synchronizations [ 15 ] . 4. EXPERIMENTAL FRAMEWORK The best publicly available , auto - parallelizing , C com- piler SUIF produces shared - memory data parallel C codes from sequential C input files and ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires