CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 49.
37. lappuse
... methodology . Consequently , this task is error prone and becomes a bottleneck in embedded system design methodology . Our solution to this problem starts by accurately specifying device access behavior with a formal model , viz ...
... methodology . Consequently , this task is error prone and becomes a bottleneck in embedded system design methodology . Our solution to this problem starts by accurately specifying device access behavior with a formal model , viz ...
163. lappuse
... methodology for security is crucial for future NoC designs and a necessity for designing with secure IP cores available on the market today . This research presents a security methodology at the network level ( or transport layer ) and ...
... methodology for security is crucial for future NoC designs and a necessity for designing with secure IP cores available on the market today . This research presents a security methodology at the network level ( or transport layer ) and ...
209. lappuse
... METHODOLOGY The application of our methodology consists of the following steps : 1. a KSOG is built starting from specifications ; 2. the KSOG is decomposed into bunches ; 3. bunches are split among levels according to their mutual ...
... METHODOLOGY The application of our methodology consists of the following steps : 1. a KSOG is built starting from specifications ; 2. the KSOG is decomposed into bunches ; 3. bunches are split among levels according to their mutual ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires