CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 56.
115. lappuse
... method called Quasi - Dynamic Scheduling ( QDS ) , which incorporates the respective solutions as briefly described in the following . • Concurrently Enabled Group : We maintain a group of con- currently enabled subtasks , while the ...
... method called Quasi - Dynamic Scheduling ( QDS ) , which incorporates the respective solutions as briefly described in the following . • Concurrently Enabled Group : We maintain a group of con- currently enabled subtasks , while the ...
199. lappuse
... method over a wide variety of working conditions , we first perform the experiments on a single bus varying the number of processors , bus request rates , bus service rates ( or memory access times ) , and burst lengths . We generate ...
... method over a wide variety of working conditions , we first perform the experiments on a single bus varying the number of processors , bus request rates , bus service rates ( or memory access times ) , and burst lengths . We generate ...
214. lappuse
... methods execution . We refer to such objects as " method local objects " . Using a trace- based escape analysis technique , we identify the method local ob- jects and turn the corresponding cache lines off when the method to which it is ...
... methods execution . We refer to such objects as " method local objects " . Using a trace- based escape analysis technique , we identify the method local ob- jects and turn the corresponding cache lines off when the method to which it is ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires