CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 88.
132. lappuse
... Memory Architecture with NAND XIP for. ABSTRACT Many of the current memory architectures embed a SRAM cache within the DRAM memory . These architectures ex- ploit a wide internal data bus to transfer an entire DRAM row to the on - memory ...
... Memory Architecture with NAND XIP for. ABSTRACT Many of the current memory architectures embed a SRAM cache within the DRAM memory . These architectures ex- ploit a wide internal data bus to transfer an entire DRAM row to the on - memory ...
138. lappuse
... memory is gaining popularity as data storage , it can be also exploited as code memory for XIP ( execute - in - place ) . In this paper , we present a new memory architecture which incorporates NAND flash memory into an existing memory ...
... memory is gaining popularity as data storage , it can be also exploited as code memory for XIP ( execute - in - place ) . In this paper , we present a new memory architecture which incorporates NAND flash memory into an existing memory ...
141. lappuse
... memory latency hiding without miss penalty from miss - prediction at run - time . Priority Caching ( address ) { page = convert ( address ) ; if ( isInPAT ( page ) ) main memory hit ; else if ( isInMainCache ( page ) ) Cache hit ; else ...
... memory latency hiding without miss penalty from miss - prediction at run - time . Priority Caching ( address ) { page = convert ( address ) ; if ( isInPAT ( page ) ) main memory hit ; else if ( isInMainCache ( page ) ) Cache hit ; else ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires