CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 77.
87. lappuse
... Mapping and Partitioning The mapping and partitioning step ( line 09 in Figure 5 ) receives as an input a configuration in which the TT activities are schedulable and the ET ones are not . The algorithm is illustrated in Figure 7. It ...
... Mapping and Partitioning The mapping and partitioning step ( line 09 in Figure 5 ) receives as an input a configuration in which the TT activities are schedulable and the ET ones are not . The algorithm is illustrated in Figure 7. It ...
182. lappuse
... mapping step to relate these models for co - simulation . So far in Sesame , the mapping decision has been assumed to be ... Mapping Function 182 A Multiobjective Optimization Model for Exploring Multiprocessor Mappings of Process Networks.
... mapping step to relate these models for co - simulation . So far in Sesame , the mapping decision has been assumed to be ... Mapping Function 182 A Multiobjective Optimization Model for Exploring Multiprocessor Mappings of Process Networks.
183. lappuse
P1 B Application Model f M 22 P2 Mapping Function Architecture Model Figure 1 : The mapping problem on a simple example . The rest of the paper is organized as follows : we model the map- ping decision in Sesame as a multiobjective ...
P1 B Application Model f M 22 P2 Mapping Function Architecture Model Figure 1 : The mapping problem on a simple example . The rest of the paper is organized as follows : we model the map- ping decision in Sesame as a multiobjective ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires
Bibliogrāfiskā informācija
| Nosaukums | CODES+ISSS |
| Atbalstītāji | Institute of Electrical and Electronics Engineers, Association for Computing Machinery, International Federation for Information Processing |
| Izdevējs | ACM Press, 2003 |
| Oriģināls no | Mičiganas universitāte |
| Digitalizēta | 10.1.2008 |
| ISBN | 1581137427, 9781581137422 |
| Eksportēt avotu | BiBTeX EndNote RefMan |