CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 51.
109. lappuse
... logic minimizer architecture. Abstract Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers . However , logic minimization has recently been proposed for dynamic use in embedded ...
... logic minimizer architecture. Abstract Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers . However , logic minimization has recently been proposed for dynamic use in embedded ...
113. lappuse
... logic minimizer . Finally , Energy Savings is the percent energy reduction of our codesigned logic minimizers compared with ROCM - 32 and ROCM - 128 . We calculated the energy required for ROCM - 32 , ROCM - 128 , and our codesigned ...
... logic minimizer . Finally , Energy Savings is the percent energy reduction of our codesigned logic minimizers compared with ROCM - 32 and ROCM - 128 . We calculated the energy required for ROCM - 32 , ROCM - 128 , and our codesigned ...
171. lappuse
... logic Output Sensor O O O Wireless Transmitter - wirelessly transmits a signal to another eBlock Wireless Receiver - wirelessly receives a signal from another eBlock 2 - Input Logic Block configurable logic block programmed by the user ...
... logic Output Sensor O O O Wireless Transmitter - wirelessly transmits a signal to another eBlock Wireless Receiver - wirelessly receives a signal from another eBlock 2 - Input Logic Block configurable logic block programmed by the user ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires