CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 28.
106. lappuse
... iterations 1 iteration Analog front - end RRC rake demux 2nd de- interleaver Pilot / control bits 1st de- interleav 1 iteration Remove DTX Bits 1 iteration Viterbi ( rate 1/2 ) 1 iteration Viterbi ( rate 1/3 ) 1 iteration 1 iteration ...
... iterations 1 iteration Analog front - end RRC rake demux 2nd de- interleaver Pilot / control bits 1st de- interleav 1 iteration Remove DTX Bits 1 iteration Viterbi ( rate 1/2 ) 1 iteration Viterbi ( rate 1/3 ) 1 iteration 1 iteration ...
145. lappuse
... iteration is the execution of each node in V exactly once . Inter- iteration dependencies are represented by weighted edges . For any iteration j , an edge e from u to v with delay d ( e ) conveys that the computation of node v at iteration ...
... iteration is the execution of each node in V exactly once . Inter- iteration dependencies are represented by weighted edges . For any iteration j , an edge e from u to v with delay d ( e ) conveys that the computation of node v at iteration ...
149. lappuse
... iteration bound B ( G ) = 3/2 . Given an iteration period con- straint P = 5/3 . an configuration satisfying the iteration period constraint is found by STDur . It has 3 adders and 16 multipliers with unfolding factor f = 4 . The ...
... iteration bound B ( G ) = 3/2 . Given an iteration period con- straint P = 5/3 . an configuration satisfying the iteration period constraint is found by STDur . It has 3 adders and 16 multipliers with unfolding factor f = 4 . The ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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