CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 66.
13. lappuse
... instruction information . LISA supports simple RISC like instruction formats and efficient support of complex instruction formats requires extensive coding in this language . In contrast , our simulation framework efficiently supports a ...
... instruction information . LISA supports simple RISC like instruction formats and efficient support of complex instruction formats requires extensive coding in this language . In contrast , our simulation framework efficiently supports a ...
227. lappuse
... instructions . This leads to not - so - good pro- gram structures that introduce higher instruction cache miss ratio . The TCP / IP protocol stack has a lower percentage of conditional branch instructions compared to SPECint benchmark ...
... instructions . This leads to not - so - good pro- gram structures that introduce higher instruction cache miss ratio . The TCP / IP protocol stack has a lower percentage of conditional branch instructions compared to SPECint benchmark ...
228. lappuse
... instruction cache with 32 - byte line size . In these baseline cases , more than half of the total exe- cution time is spent in waiting for completion of data or instruction accesses . Instruction access time is at least 3 to 4 times ...
... instruction cache with 32 - byte line size . In these baseline cases , more than half of the total exe- cution time is spent in waiting for completion of data or instruction accesses . Instruction access time is at least 3 to 4 times ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires