CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 61.
3. lappuse
... input event arrives while the component processes the current event . Since a software simulator may accept the input event after completion of the current execution . Then , the time stamp of the output event would be t1 + A ( d1 ) + A ...
... input event arrives while the component processes the current event . Since a software simulator may accept the input event after completion of the current execution . Then , the time stamp of the output event would be t1 + A ( d1 ) + A ...
171. lappuse
... input is a yes . Device emits no light when input Device receives a signal and replicates that signal on each output . An input of yes toggles ( inverts ) the current value outputted by the device . Configurable logic block programmed ...
... input is a yes . Device emits no light when input Device receives a signal and replicates that signal on each output . An input of yes toggles ( inverts ) the current value outputted by the device . Configurable logic block programmed ...
172. lappuse
... Input Logic eBlock ( c ) Output Block - Green / Red LED eBlock ( a ) IX rx ( b ) 4.2 Computers in Every Block ( c ) ... input signal into a stop bit . To support packets , every block must contain a simple computer , as shown in Figure 2 ...
... Input Logic eBlock ( c ) Output Block - Green / Red LED eBlock ( a ) IX rx ( b ) 4.2 Computers in Every Block ( c ) ... input signal into a stop bit . To support packets , every block must contain a simple computer , as shown in Figure 2 ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires