CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 52.
226. lappuse
... improve processing of non - data- touching operations . Hence , we primarily focus on reducing the latencies for non - data - touching operations . In this paper , we take TCP / IP protocol processing as an inde- pendent workload and ...
... improve processing of non - data- touching operations . Hence , we primarily focus on reducing the latencies for non - data - touching operations . In this paper , we take TCP / IP protocol processing as an inde- pendent workload and ...
227. lappuse
... improvement on both CPU execution time and instruction cache when ILP increases . However , for TCP / IP protocol processing , it does not improve data or instruction access time very much . For instance , the total execution time of ...
... improvement on both CPU execution time and instruction cache when ILP increases . However , for TCP / IP protocol processing , it does not improve data or instruction access time very much . For instance , the total execution time of ...
230. lappuse
... improve the perfor- mance . 6. CONCLUSION In order to evaluate the performance of TCP / IP protocol and study the headroom of improving protocol processing latency , we ported the complete TCP / IP protocol stack from FreeBSD operat ...
... improve the perfor- mance . 6. CONCLUSION In order to evaluate the performance of TCP / IP protocol and study the headroom of improving protocol processing latency , we ported the complete TCP / IP protocol stack from FreeBSD operat ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires