CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 90.
20. lappuse
... implementation model by adding implementation de- tails . In comparison to the top - down approaches , meet- in - the - middle approaches [ 13 ] map the system behavior to the predefined system architecture , rather than generating the ...
... implementation model by adding implementation de- tails . In comparison to the top - down approaches , meet- in - the - middle approaches [ 13 ] map the system behavior to the predefined system architecture , rather than generating the ...
22. lappuse
... Implementation model cycle - accurate pin - accurate PE4 ( Arbiter ) PE3 PE1 3 B1 v1 = a * a ; cv12 cv2 2 │PE2 cv11 ... Implementation model . It has both cycle - accurate communication and cycle - accurate computation . The com ...
... Implementation model cycle - accurate pin - accurate PE4 ( Arbiter ) PE3 PE1 3 B1 v1 = a * a ; cv12 cv2 2 │PE2 cv11 ... Implementation model . It has both cycle - accurate communication and cycle - accurate computation . The com ...
102. lappuse
... implementation described in this work with and without embedded compression . The implementation supports up to CIF @ 30fps . The motion estimator , the texture , and the packer processors where synthesized as hardware components for ...
... implementation described in this work with and without embedded compression . The implementation supports up to CIF @ 30fps . The motion estimator , the texture , and the packer processors where synthesized as hardware components for ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires