CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 89.
25. lappuse
... hardware design and synthesis based on SystemC . We will give an introduction to an extended SystemC synthesis sub- set which we propose , and , in particular , its object - oriented features . We will also briefly outline our basic ...
... hardware design and synthesis based on SystemC . We will give an introduction to an extended SystemC synthesis sub- set which we propose , and , in particular , its object - oriented features . We will also briefly outline our basic ...
99. lappuse
... hardware processing tasks . e ) Partially implemented cycle - true hardware level ; bit- and cycle - true models for the communication , bit- and cycle- true functional models for software and hardware processing tasks , combined with ...
... hardware processing tasks . e ) Partially implemented cycle - true hardware level ; bit- and cycle - true models for the communication , bit- and cycle- true functional models for software and hardware processing tasks , combined with ...
100. lappuse
... hardware , which corresponds to translation from level ' b ' to ' c ' in Figure 2. This is done as follows : The input variables of the hardware processors consist of two parts : initialization variables ( e.g. number of pixels in ...
... hardware , which corresponds to translation from level ' b ' to ' c ' in Figure 2. This is done as follows : The input variables of the hardware processors consist of two parts : initialization variables ( e.g. number of pixels in ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires