CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 85.
95. lappuse
... given by a tuple PN = ( P , C ) where : P = { P1 = 1 .. | P | } is a set of processes . C = { Cj = 1 .. | c | } is a set of channels . Definition 3.9 ( process ) = A process in the PN is given by a tuple P = ( NP , IP , OP , ST ) where ...
... given by a tuple PN = ( P , C ) where : P = { P1 = 1 .. | P | } is a set of processes . C = { Cj = 1 .. | c | } is a set of channels . Definition 3.9 ( process ) = A process in the PN is given by a tuple P = ( NP , IP , OP , ST ) where ...
128. lappuse
... given resource constraint for power optimization can be given as , FS ( m ) = { x : m⋅ x ≤ w } ( 3 ) where , FS ( m ) is the feasibility set for all the operations and their resources and m is the cost vector corresponding to the ...
... given resource constraint for power optimization can be given as , FS ( m ) = { x : m⋅ x ≤ w } ( 3 ) where , FS ( m ) is the feasibility set for all the operations and their resources and m is the cost vector corresponding to the ...
129. lappuse
... given as , b ( 1 , 1 ) = co ( 1 , 1 ) . The general- ized cost matrix CM of size x , x yj is given as , operations scheduled during control step i architecture number of operations of type j in the architecture set of all modules of ...
... given as , b ( 1 , 1 ) = co ( 1 , 1 ) . The general- ized cost matrix CM of size x , x yj is given as , operations scheduled during control step i architecture number of operations of type j in the architecture set of all modules of ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires