CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 47.
7. lappuse
... exploration of the on - chip communication architecture to meet per- formance and cost requirements . Based on SystemC 2.0.1 we have defined a modular exploration framework , which is able to capture the effect on performance for ...
... exploration of the on - chip communication architecture to meet per- formance and cost requirements . Based on SystemC 2.0.1 we have defined a modular exploration framework , which is able to capture the effect on performance for ...
8. lappuse
... exploration and profiling driven partitioning of large - scale systems with complex and heterogeneous communication schemes . The following section discusses related work in the area of explo- ration of system level communication ...
... exploration and profiling driven partitioning of large - scale systems with complex and heterogeneous communication schemes . The following section discusses related work in the area of explo- ration of system level communication ...
11. lappuse
... exploration of the communication architecture . An excerpt of the NoC exploration results is printed in table 3. Besides the engine - descriptor and -configuration we list the resource utiliza- tion and the mean delay per transaction of ...
... exploration of the communication architecture . An excerpt of the NoC exploration results is printed in table 3. Besides the engine - descriptor and -configuration we list the resource utiliza- tion and the mean delay per transaction of ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires