CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 88.
13. lappuse
... example , the dest symbol ( in Example 1 ) is from 25th to 29th bits in the instruction , and is an integer register . Its type can be described as : DestType = [ IntegerRegClass , 29 , 25 ] . Similarly a portion of an instruction may ...
... example , the dest symbol ( in Example 1 ) is from 25th to 29th bits in the instruction , and is an integer register . Its type can be described as : DestType = [ IntegerRegClass , 29 , 25 ] . Similarly a portion of an instruction may ...
29. lappuse
... example a classical producer / consumer sys- tem is modelled which is also often used as an example for demonstrating the benefits of channels in SystemC . Pro- ducer and consumer are exchanging data via a bounded buffer , which ...
... example a classical producer / consumer sys- tem is modelled which is also often used as an example for demonstrating the benefits of channels in SystemC . Pro- ducer and consumer are exchanging data via a bounded buffer , which ...
118. lappuse
... Example else return True ; } ( 12 ) else if ( empty ( G ) ) { ( 13 ) G ' = Glast ; return True ; } ( 14 ) else { ( 15 ) Grime = 0 ; ( 15 ) Table 4 : QDS scheduling for R12 and R21 n G α Ρ STime SMem G fire next for each transition tЄG ...
... Example else return True ; } ( 12 ) else if ( empty ( G ) ) { ( 13 ) G ' = Glast ; return True ; } ( 14 ) else { ( 15 ) Grime = 0 ; ( 15 ) Table 4 : QDS scheduling for R12 and R21 n G α Ρ STime SMem G fire next for each transition tЄG ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires