CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 56.
187. lappuse
... evaluate a large design space and provide us a number of approximated Pareto - optimal solutions . These solutions are then input to our simulation framework for further evaluation . After simulation , figures about system - level trade ...
... evaluate a large design space and provide us a number of approximated Pareto - optimal solutions . These solutions are then input to our simulation framework for further evaluation . After simulation , figures about system - level trade ...
214. lappuse
... evaluate our energy optimization schemes that use garbage collection , escape analysis and last - use analysis in Sections 4 through 6. In Section 7 , we present how to optimize energy consumed by live objects . Fi- nally , we provide ...
... evaluate our energy optimization schemes that use garbage collection , escape analysis and last - use analysis in Sections 4 through 6. In Section 7 , we present how to optimize energy consumed by live objects . Fi- nally , we provide ...
226. lappuse
... evaluate the optimization for , TCP / IP protocol processing . It is observed that the instruction cache has a greater impact on TCP / IP performance . In order to improve effectiveness of an in- struction cache , we identify the ...
... evaluate the optimization for , TCP / IP protocol processing . It is observed that the instruction cache has a greater impact on TCP / IP performance . In order to improve effectiveness of an in- struction cache , we identify the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires