CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 40.
196. lappuse
... estimation . As the static estimation gets more accurate , the design space to be explored by simulation would be narrower . The key contribution of this paper is to propose an accurate static estimation method taking into account of ...
... estimation . As the static estimation gets more accurate , the design space to be explored by simulation would be narrower . The key contribution of this paper is to propose an accurate static estimation method taking into account of ...
199. lappuse
... estimation technique after λ and computation . Therefore the static estimation and bridge modeling are performed iteratively until all parameters become stable . PE μsrc λ dest bridge W destbus We dest src SIC bus Hdest Mem Figure 5 ...
... estimation technique after λ and computation . Therefore the static estimation and bridge modeling are performed iteratively until all parameters become stable . PE μsrc λ dest bridge W destbus We dest src SIC bus Hdest Mem Figure 5 ...
200. lappuse
... estimation method execution time by 85 % due to serious bus contentions . Consequently Arch 2 is faster than Arch 1 by about 30 % . Table 5. Experimental results about DVR Architecture candidates Schedule Ideal Simulation Arch 1 Arch 2 ...
... estimation method execution time by 85 % due to serious bus contentions . Consequently Arch 2 is faster than Arch 1 by about 30 % . Table 5. Experimental results about DVR Architecture candidates Schedule Ideal Simulation Arch 1 Arch 2 ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires