CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 34.
213. lappuse
... energy consumed in the data caches when executing embedded Java applications . Our anal- ysis reveals that a major portion of the leakage energy is actually wasted in retaining the objects beyond their last use . In order to eliminate ...
... energy consumed in the data caches when executing embedded Java applications . Our anal- ysis reveals that a major portion of the leakage energy is actually wasted in retaining the objects beyond their last use . In order to eliminate ...
214. lappuse
... energy - constrained mobile devices [ 7 , 8 ] . The results of our evaluation of using ten embedded Java applications shows that the three proposed approaches provide significant savings in leakage energy consumption . The remainder of ...
... energy - constrained mobile devices [ 7 , 8 ] . The results of our evaluation of using ten embedded Java applications shows that the three proposed approaches provide significant savings in leakage energy consumption . The remainder of ...
215. lappuse
... energy consumption breakdown as dynamic energy and static energy com- ponents . The static energy part is further divided into energies ex- pended in different cache line states . This graph clearly shows that a large percentage of the ...
... energy consumption breakdown as dynamic energy and static energy com- ponents . The static energy part is further divided into energies ex- pended in different cache line states . This graph clearly shows that a large percentage of the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires