CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 18.
36. lappuse
... encoder [ 7 ] . Table 1 shows the results for the vocoder model . The vocoder models were exercised by a testbench that feeds a stream of 163 speech frames corresponding to 3.26 s of speech into encoder and decoder . The transcoding ...
... encoder [ 7 ] . Table 1 shows the results for the vocoder model . The vocoder models were exercised by a testbench that feeds a stream of 163 speech frames corresponding to 3.26 s of speech into encoder and decoder . The transcoding ...
97. lappuse
... encoder . In the architectural front , an efficient hardware - software partitioning has contributed to the design of a low - power encoder . Further , the hardware components that accelerate the kernels of encoding are implemented as ...
... encoder . In the architectural front , an efficient hardware - software partitioning has contributed to the design of a low - power encoder . Further , the hardware components that accelerate the kernels of encoding are implemented as ...
102. lappuse
... encoder implementation described in this work with and without embedded compression . The implementation supports up ... encoder was verified ( bit - true and cycle - true ) until the netlist . Table 4.1 . Area / Power Numbers of Encoder ...
... encoder implementation described in this work with and without embedded compression . The implementation supports up ... encoder was verified ( bit - true and cycle - true ) until the netlist . Table 4.1 . Area / Power Numbers of Encoder ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires