CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 86.
vii. lappuse
... Embedded Software with Local and Global Deadlines 114 P.-A. Hsiung , C.-Y. Lin ( National Chung Cheng University ) • Pareto - Optimization - Based Run - Time Task Scheduling for Embedded Systems ...
... Embedded Software with Local and Global Deadlines 114 P.-A. Hsiung , C.-Y. Lin ( National Chung Cheng University ) • Pareto - Optimization - Based Run - Time Task Scheduling for Embedded Systems ...
138. lappuse
... embedded systems because of its versatile features such as non - volatility , solid - state reliability , low cost and high density . Even though NAND flash memory is gaining popularity as data storage , it can be also exploited as code ...
... embedded systems because of its versatile features such as non - volatility , solid - state reliability , low cost and high density . Even though NAND flash memory is gaining popularity as data storage , it can be also exploited as code ...
168. lappuse
... Embedded Computer Systems at UC Irvine Table 1 : Partial Boolean eBlock Catalog Determines when contact. Abstract - We describe our first efforts to develop a set of off - the - shelf hardware components that ordinary people could ...
... Embedded Computer Systems at UC Irvine Table 1 : Partial Boolean eBlock Catalog Determines when contact. Abstract - We describe our first efforts to develop a set of off - the - shelf hardware components that ordinary people could ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires