CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 43.
63. lappuse
... elements of the GF ( 28 ) . Each bank will keep the necessary elements and their power , since we need up to 8 power of each element to reduce the computation time . In fact memory hierarchy is one of the important feature of the ...
... elements of the GF ( 28 ) . Each bank will keep the necessary elements and their power , since we need up to 8 power of each element to reduce the computation time . In fact memory hierarchy is one of the important feature of the ...
156. lappuse
... elements , most likely organized around an on - chip network . Thus , SoCs are increasingly modeled as systems in the large . But a chip also has a fixed set of programmable hardware elements that are much more closely coupled than for ...
... elements , most likely organized around an on - chip network . Thus , SoCs are increasingly modeled as systems in the large . But a chip also has a fixed set of programmable hardware elements that are much more closely coupled than for ...
190. lappuse
... elements of P , with the index d 0 are used to indicate the probability of permanent faults . Since the matrix elements describe the probabilities of different characteristics of one fault occurrence , their values must satisfy the ...
... elements of P , with the index d 0 are used to indicate the probability of permanent faults . Since the matrix elements describe the probabilities of different characteristics of one fault occurrence , their values must satisfy the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires