CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 12.
93. lappuse
... ( edge ) An edge in the ADG is a triple E = ( q , p , M ) where : q = ( Vq , Aq , OPDq ) is an output port . p = ( Vp , Ap , IPDp ) is an input port . Vp = Vq , i.e. , variables V and V have the same names and equal dimensions . Mipiq is ...
... ( edge ) An edge in the ADG is a triple E = ( q , p , M ) where : q = ( Vq , Aq , OPDq ) is an output port . p = ( Vp , Ap , IPDp ) is an input port . Vp = Vq , i.e. , variables V and V have the same names and equal dimensions . Mipiq is ...
145. lappuse
... edge e from u to v with delay d ( e ) conveys that the computation of node v at iteration j depends on the execution of node u at iteration j - d ( e ) . An edge with no delay represents a data dependency within the same iteration . An ...
... edge e from u to v with delay d ( e ) conveys that the computation of node v at iteration j depends on the execution of node u at iteration j - d ( e ) . An edge with no delay represents a data dependency within the same iteration . An ...
208. lappuse
... edge ( AƆ B ) whenever the SO named A contains the SO named B ( that is , B is defined inside the A , like a process can be defined inside an architecture ) ; connecting node A to node B with references - type edge ( A → B ) when SO A ...
... edge ( AƆ B ) whenever the SO named A contains the SO named B ( that is , B is defined inside the A , like a process can be defined inside an architecture ) ; connecting node A to node B with references - type edge ( A → B ) when SO A ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires