CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 63.
83. lappuse
... Distributed embedded systems implemented with mixed , event- triggered and time - triggered task sets , which communicate over bus protocols consisting of both static and dynamic phases , are emerging as the new standard in application ...
... Distributed embedded systems implemented with mixed , event- triggered and time - triggered task sets , which communicate over bus protocols consisting of both static and dynamic phases , are emerging as the new standard in application ...
161. lappuse
... Distributed Control Flow Consider the central controller of Figure 9. While many programming models include the controller as a PE , SoCs afford the possibility that the state and functionality upon which control flow decisions are made ...
... Distributed Control Flow Consider the central controller of Figure 9. While many programming models include the controller as a PE , SoCs afford the possibility that the state and functionality upon which control flow decisions are made ...
224. lappuse
... distributed address spaces and require complex run - time bookkeeping . In [ 2 ] , data tiling is used to improve spatial locality but the represen- tation does not allow easy integration with other loop and data transformations . An ...
... distributed address spaces and require complex run - time bookkeeping . In [ 2 ] , data tiling is used to improve spatial locality but the represen- tation does not allow easy integration with other loop and data transformations . An ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires