CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 49.
38. lappuse
... the function they implement . Sub - devices may share a physical interface ( ITF ) . The access of each sub - device is modeled in two User Device control Data access layers . The first layer is the device programming interface 38.
... the function they implement . Sub - devices may share a physical interface ( ITF ) . The access of each sub - device is modeled in two User Device control Data access layers . The first layer is the device programming interface 38.
39. lappuse
... device memory and register accesses are modeled through aggregating data structures and access functions . For ... device programming interface layer and the access function of the FIFO is automatically synthesized from the model . The ...
... device memory and register accesses are modeled through aggregating data structures and access functions . For ... device programming interface layer and the access function of the FIFO is automatically synthesized from the model . The ...
44. lappuse
... device controller and the port access state machines . Line discipline ( a special terminal interface ) and network interface are defined for the driver . Because the infrared port matches the model of the line discipline model ...
... device controller and the port access state machines . Line discipline ( a special terminal interface ) and network interface are defined for the driver . Because the infrared port matches the model of the line discipline model ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires