CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 48.
79. lappuse
... developed in - house ( or contracted to suppliers ) , in order to accelerate product design and , more frequently , to support the use and programming of complex SoC's by their customers . This situation is reminiscent of the mid - 80's ...
... developed in - house ( or contracted to suppliers ) , in order to accelerate product design and , more frequently , to support the use and programming of complex SoC's by their customers . This situation is reminiscent of the mid - 80's ...
176. lappuse
... developed for system level de- sign . Starting with a formal specification model that captures the functionality of the system at a high abstraction level , it provides formal design transformation methods for a transparent refinement ...
... developed for system level de- sign . Starting with a formal specification model that captures the functionality of the system at a high abstraction level , it provides formal design transformation methods for a transparent refinement ...
182. lappuse
... develop a modeling and simulation environment for the efficient design space exploration of hetero- geneous embedded ... developed to achieve a set of best alternative mapping decisions under multiple criteria . In a case study , we have ...
... develop a modeling and simulation environment for the efficient design space exploration of hetero- geneous embedded ... developed to achieve a set of best alternative mapping decisions under multiple criteria . In a case study , we have ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires