CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 50.
13. lappuse
... described in Section 3.1 . Using the instruction specifications from ADL , the Static Instruction Decoder decodes the target program one instruction at a time , as described in Section 3.2 . It then generates the optimized source code ...
... described in Section 3.1 . Using the instruction specifications from ADL , the Static Instruction Decoder decodes the target program one instruction at a time , as described in Section 3.2 . It then generates the optimized source code ...
15. lappuse
... described in [ 2 ] . Figure 5 shows the extracted template and its parameters for data- processing instructions in ARM , described in Figure 4 . / * extracted template for data processing operations of ARM * / template < class ...
... described in [ 2 ] . Figure 5 shows the extracted template and its parameters for data- processing instructions in ARM , described in Figure 4 . / * extracted template for data processing operations of ARM * / template < class ...
224. lappuse
... described how DSP programs may be parallelized but gave no details or experimental results . Similarly , in [ 8 ] an interesting overall parallelization frame- work is described but no mechanism or details of how paral- lelization might ...
... described how DSP programs may be parallelized but gave no details or experimental results . Similarly , in [ 8 ] an interesting overall parallelization frame- work is described but no mechanism or details of how paral- lelization might ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires