CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 52.
35. lappuse
... delay * / os.time_wait ( BLOCK2_DELAY ) ; / * model delay * / os.task_terminate ( h ) ; b3 . main ( ) ; 11 b2.main ( ) : b3.main ( ) ; ; } 12 } 13 os.join ( t ) ; } 14 } ( a ) before ( b ) after Figure 6 : Task creation 1 channel C1 ...
... delay * / os.time_wait ( BLOCK2_DELAY ) ; / * model delay * / os.task_terminate ( h ) ; b3 . main ( ) ; 11 b2.main ( ) : b3.main ( ) ; ; } 12 } 13 os.join ( t ) ; } 14 } ( a ) before ( b ) after Figure 6 : Task creation 1 channel C1 ...
47. lappuse
... delay field is 16 bits wide . Each record uses 40 bits of storage but is mapped into the I / O space at even - word ... Delay ( 16 ) Delayed Event Suspended Reserved ( 4 ) The RTM is pictured in Figure 1 ; where each record contains ...
... delay field is 16 bits wide . Each record uses 40 bits of storage but is mapped into the I / O space at even - word ... Delay ( 16 ) Delayed Event Suspended Reserved ( 4 ) The RTM is pictured in Figure 1 ; where each record contains ...
48. lappuse
... delay decrement cells are all that is required , as shown in Figure 3. Delay decrement cells consists of a simplified 16 - bit adder and an AND gate . Delay cells decrement the delay field and perform a comparison to clear the delay bit ...
... delay decrement cells are all that is required , as shown in Figure 3. Delay decrement cells consists of a simplified 16 - bit adder and an AND gate . Delay cells decrement the delay field and perform a comparison to clear the delay bit ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires