CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 21.
38. lappuse
... data path accesses to provide a higher level abstraction which enables cleaner specification and more efficient checking . While our earlier publication [ 1 ] gives an overview of the overall methodology , this paper focuses on the ...
... data path accesses to provide a higher level abstraction which enables cleaner specification and more efficient checking . While our earlier publication [ 1 ] gives an overview of the overall methodology , this paper focuses on the ...
131. lappuse
... data - path circuits as we move into deep sub - micron and nano regimes . 6 . REFERENCES [ 1 ] A. Dasgupta and R. Karri . Simultaneous scheduling and binding for power minimization during micro - architecture synthesis . In Proc . Intl ...
... data - path circuits as we move into deep sub - micron and nano regimes . 6 . REFERENCES [ 1 ] A. Dasgupta and R. Karri . Simultaneous scheduling and binding for power minimization during micro - architecture synthesis . In Proc . Intl ...
230. lappuse
... path - inlining to reduce processing latency by improving the instruction ... data movement . This solution has been explored in much de- tail . One ... data sets of TCP / IP . We also extended SimpleScalar simulation environment by di ...
... path - inlining to reduce processing latency by improving the instruction ... data movement . This solution has been explored in much de- tail . One ... data sets of TCP / IP . We also extended SimpleScalar simulation environment by di ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires