CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 81.
78. lappuse
... cycles needed to communicate across the chip ) such that registers in bank i will hold the results for i cycles for communicating with another island that is i cycles away . 3 ) Finite State Machine ( FSM ) : Each island contains a ...
... cycles needed to communicate across the chip ) such that registers in bank i will hold the results for i cycles for communicating with another island that is i cycles away . 3 ) Finite State Machine ( FSM ) : Each island contains a ...
131. lappuse
... cycles mW cycles w.r.t. SL S cycles mW w.r.t. SL S Diff . eqn 2,2 4 26.5 4 6.4 18 5 23.9 9.8 22 FIR 3.3 9 99.7 9 16.9 113 10 78.7 21.1 107 IIR 2,2 8 18.9 8 17.4 48 9 14.8 21.7 52 Lattice 3.3 8 121.0 9 24.5 105 9 82.9 31.5 90 EWF 2,2 16 ...
... cycles mW cycles w.r.t. SL S cycles mW w.r.t. SL S Diff . eqn 2,2 4 26.5 4 6.4 18 5 23.9 9.8 22 FIR 3.3 9 99.7 9 16.9 113 10 78.7 21.1 107 IIR 2,2 8 18.9 8 17.4 48 9 14.8 21.7 52 Lattice 3.3 8 121.0 9 24.5 105 9 82.9 31.5 90 EWF 2,2 16 ...
190. lappuse
... cycles . 0 0.65 0.1 0.2 0.05 P2 = ( meaning that a fault of type f2 will be confined to one wire and one clock ( or transfer ) cycle in 65 % of all occurrences . Another 20 % of these faults will disturb two wires for one clock cycle ...
... cycles . 0 0.65 0.1 0.2 0.05 P2 = ( meaning that a fault of type f2 will be confined to one wire and one clock ( or transfer ) cycle in 65 % of all occurrences . Another 20 % of these faults will disturb two wires for one clock cycle ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires