CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 81.
21. lappuse
... cycle - accurate cycle - accurate. PE1 B1 v1 = a * a ; PE4 ( Arbiter ) PE3 ready ack ( 5 , 15 ) ( 5,25 ) B3 ( 10,20 ) v3 = v1- b * b ; cv12 cv2 v3 PE2 CV11 B4 B2 v4 = v2 + v3 ; v2 = v1 + b * b ; c = sequ ( v4 ) ; 1. Master interface 2 ...
... cycle - accurate cycle - accurate. PE1 B1 v1 = a * a ; PE4 ( Arbiter ) PE3 ready ack ( 5 , 15 ) ( 5,25 ) B3 ( 10,20 ) v3 = v1- b * b ; cv12 cv2 v3 PE2 CV11 B4 B2 v4 = v2 + v3 ; v2 = v1 + b * b ; c = sequ ( v4 ) ; 1. Master interface 2 ...
22. lappuse
approximate Computation approximate approximate cycle - accurate cycle - accurate wire Table 1 : Characteristics of different abstraction models Extending the SystemC Synthesis Subset by Object - Oriented Features. Models Specification ...
approximate Computation approximate approximate cycle - accurate cycle - accurate wire Table 1 : Characteristics of different abstraction models Extending the SystemC Synthesis Subset by Object - Oriented Features. Models Specification ...
77. lappuse
... cycle full chip synchronization is no longer possible , which is about to happen soon . It can been shown that , even with the aggressive interconnect optimization techniques ( e.g. , buffer insertion and wire - sizing ) , 5 clock cycles ...
... cycle full chip synchronization is no longer possible , which is about to happen soon . It can been shown that , even with the aggressive interconnect optimization techniques ( e.g. , buffer insertion and wire - sizing ) , 5 clock cycles ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires