CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 41.
104. lappuse
... Core Controller determines the application's control flow , executes the sequential tasks of the application , and starts transfers to / from the off - core memory . The instructions for the mRISC are stored in the Instruction Memory ...
... Core Controller determines the application's control flow , executes the sequential tasks of the application , and starts transfers to / from the off - core memory . The instructions for the mRISC are stored in the Instruction Memory ...
162. lappuse
... cores and NoC . This is crucial to prevent untrusted software on or off the NoC from gaining access to keys . At the core level ( application layer ) power analysis attacks are examined for the first time for parallel and adiabatic ...
... cores and NoC . This is crucial to prevent untrusted software on or off the NoC from gaining access to keys . At the core level ( application layer ) power analysis attacks are examined for the first time for parallel and adiabatic ...
163. lappuse
... core level ( or application layer ) . At the network level the security design utilizes a special key - keeper core and a network key on the NoC . This security architecture is independent of the type of communication network on the ...
... core level ( or application layer ) . At the network level the security design utilizes a special key - keeper core and a network key on the NoC . This security architecture is independent of the type of communication network on the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires