CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–2. rezultāts no 2.
112. lappuse
... coprocessor using Design Compiler and gate - level simulations . The CD - ROCM - 32 coprocessor required roughly 19,000 gates and has a power consumption of 100 mW when active . The CD - ROCM - 128 Minimization Coprocessor ( b ) ...
... coprocessor using Design Compiler and gate - level simulations . The CD - ROCM - 32 coprocessor required roughly 19,000 gates and has a power consumption of 100 mW when active . The CD - ROCM - 128 Minimization Coprocessor ( b ) ...
113. lappuse
... Coprocessor . Proc . Field - Programmable Custom Computing Machines ( FCCM ) , 1997 . [ 5 ] Cong , J. , J. Peck . On Acceleration on the Check Tautology Logic Synthesis Algorithm using an FPGA - based Reconfigurable Coprocessor ...
... Coprocessor . Proc . Field - Programmable Custom Computing Machines ( FCCM ) , 1997 . [ 5 ] Cong , J. , J. Peck . On Acceleration on the Check Tautology Logic Synthesis Algorithm using an FPGA - based Reconfigurable Coprocessor ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires