CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 47.
69. lappuse
... consumption of speech recognition , we integrated the Wattch power analysis tool [ 14 ] with the IMPACT architecture simulator . Figure 2 illustrates the power consumption for the architecture studied through the duration of the sample ...
... consumption of speech recognition , we integrated the Wattch power analysis tool [ 14 ] with the IMPACT architecture simulator . Figure 2 illustrates the power consumption for the architecture studied through the duration of the sample ...
139. lappuse
... consumption over existing memory architectures . Finally , our conclusions and future work are drawn in Section 7 ... consumption from power hungry DRAM memory is another problem for battery - operated systems . Thus , it is important to ...
... consumption over existing memory architectures . Finally , our conclusions and future work are drawn in Section 7 ... consumption from power hungry DRAM memory is another problem for battery - operated systems . Thus , it is important to ...
213. lappuse
... consumption due to leakage current is an important concern in future technologies [ 1 ] . Unlike dynamic energy consumption , static power is consumed independent of whether the component * This research is supported in part by NSF ...
... consumption due to leakage current is an important concern in future technologies [ 1 ] . Unlike dynamic energy consumption , static power is consumed independent of whether the component * This research is supported in part by NSF ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires