CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 51.
78. lappuse
... constraints Multi - cycle path constraints Figure 2. MCAS architectural synthesis system Given the target clock period and the RDR architecture specification ( including the island structure , functional unit library and delay table ) ...
... constraints Multi - cycle path constraints Figure 2. MCAS architectural synthesis system Given the target clock period and the RDR architecture specification ( including the island structure , functional unit library and delay table ) ...
116. lappuse
... constraints are classified into two categories : local deadlines and global deadlines . A local deadline is imposed on the execution of a subtask , whereas a global deadline is imposed on the execution of a task in a system model [ 11 ] ...
... constraints are classified into two categories : local deadlines and global deadlines . A local deadline is imposed on the execution of a subtask , whereas a global deadline is imposed on the execution of a task in a system model [ 11 ] ...
185. lappuse
... constraints of the problem . For genes representing Kahn process nodes , only the set of processors at the architecture model form the allele set , while for genes representing the FIFO channels , both the set of processors and the set ...
... constraints of the problem . For genes representing Kahn process nodes , only the set of processors at the architecture model form the allele set , while for genes representing the FIFO channels , both the set of processors and the set ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires